1. Field of the Invention
This invention relates to non-volatile semiconductor memories, and in particular, to improving the endurance of such memories.
2. Description of Related Art
Non-volatile semiconductor memories such as EPROMs, EEPROMs, and Flash memories are well known. In such memories, a threshold voltage Vt of a memory cell indicates a data value stored in the memory cell. When writing (programming) to a selected memory cell in a conventional non-volatile memory array, programming voltages are applied via a word-line (WL) connected to a control gate of the selected cell, via a bit-line (BL) connected to a drain of the selected cell, and a via source-line (SL) coupled to a source of the selected cell. The combination of programming voltages changes the threshold voltage of the selected cell, typically by causing Fowler-Nordheim (F-N) tunneling or channel hot electron (CHE) injection which charges (or discharges) a floating gate in the selected memory cell.
For example, to induce CHE injection in a selected memory cell containing a typical N-channel floating gate transistor, a high voltage Vpp (e.g., approximately 9 to 12 volts or higher) is applied as the control gate voltage Vg to the WL containing the selected cell, a high voltage (e.g., approximately 4.5 to 5.5 volts or higher) is applied as the drain voltage Vd to the BL containing the selected cell, and a low voltage (e.g., near 0 volt) is applied as the source voltage Vs to the SLs. Hot electrons are injected into the floating gate to increase the threshold level with respect to the control gate, thereby programming the selected cell. By adjusting the programming voltage Vpp and/or duration of the pulse, the selected cell can be programmed to a desired threshold voltage Vt.
Memory cells in conventional Flash memory arrays are typically simultaneously erased, by sectors, blocks, or full-chip, so that all of the cells in the array connected to a common source line are simultaneously erased. Memory cells are erased by discharging the floating gate, which is typically accomplished through Fowler-Nordheim tunneling by creating a large positive voltage difference from the source to the gate of the floating gate transistor, while floating the drain. Suitable voltages, which are well known, are applied to the WLs, BLs, and SLs of the array to supply voltages to the control gate, drain, and source, respectively, of memory cells in the array. These voltages cause electrons to tunnel from the floating gate to the source via Fowler-Nordheim tunneling, thereby returning the cell to an erased state.
However, erase characteristics of non-volatile memory cells are typically somewhat random and difficult to control. The key controllable parameters include tunnel oxide thickness and uniformity of the memory cell, erase voltage, erase time, and the number of cells in a sector which are erased together. In Flash memory arrays, cells connected to a common source line are erased for the same amount of time. Ideally, each cell in the array requires the same amount of time to erase, i.e., to remove electrons from the floating gate and achieve the same lower selected erased threshold voltage. However, practically, individual memory cells have slightly different characteristics, which require slightly different erase conditions to achieve the same erased threshold voltage Vte. Thus, even with existing erase and Vt monitor algorithms, some faster cells (referred to herein as fast-erase cells) may potentially become over-erased, thereby generating excessive positive charge on the floating gate and lowering the erased threshold voltage of the memory cell. In some situations of over-erasing, the erased threshold voltage becomes negative. This can be problematic in numerous ways, including during a read or verify operation.
For a read or verify operation on a selected memory cell, typically 0 volt or ground is applied as the control gate voltage Vg to unselected WLs, i.e., WLs that do not contain the selected cell.
Simultaneously, a fixed read voltage (for conventional memories) or a ramped or stepped read voltage (for analog or multi-bit-per-cell memories) is applied as the control gate voltage Vg to the selected WL for a read operation. For a verify operation, a verify voltage between the two possible threshold voltages representing a "1" and "0" (for conventional memories) or a verify voltage proportional to the desired programmed threshold voltage (for analog or multi-bit-per-cell memories) is applied as the control gate voltage Vg to the selected WL. Some verify operations are described in commonly-owned U.S. Pat. No. 5,687,115, entitled "Write Circuits For Analog Memory" to Wong et al. and U.S. Pat. No. 5,818,757, entitled "Analog and Multi-Level Memory With Reduced Program Disturb" to So et al., and in commonly-owned U.S. patent application Ser. No. 09/128,225, entitled "High Data Rate Write Processes for Non-Volatile Flash Memories, filed Aug. 3, 1998 and Ser. No. 09/224,656, entitled "Dynamic Write Process for High Bandwidth Multiple-Bit-Per-Cell and Analog Non-Volatile Memories, filed Dec. 31, 1998, all of which are incorporated by reference in their entirety.
During a read operation, for conventional memories, a fixed voltage (e.g., approximately supply voltage Vcc) is applied to the control gate of the selected cell, and for analog or multi-bit-per-cell memories, the voltage applied to the control gate of the selected cell is ramped or stepped until the selected memory cell conducts, i.e., when the voltage at the control gate is at or exceeds the threshold voltage of the cell. For an analog/multi-level memory, the voltage is slowly ramped from low to high or high to low voltages, such as described in commonly-owned U.S. Pat. No. 5,687,115, entitled "Write Circuits For Analog Memory", which is incorporated above and U.S. Pat. No. 5,751,635, entitled "Read Circuits For Analog Memory Cells" to Wong et al., which is incorporated by reference in its entirety. For a multi-bit-per-cell memory, the read voltage is increased or decreased in stepped increments using a counter scheme, such as described in commonly-owned U.S. patent application Ser. No. 09/053,716, entitled "High Resolution Multi-Bit-Per-Cell Memory", which is incorporated by reference in its entirety. For a ramped or stepped voltage, the voltage at which the cell conducts represents the analog value stored in the cell. However, erased cells in the same column as the selected cell may contribute sufficient leakage current to the bit-line of the selected cell and cause errors during read or verify operations. As a result, even when 0 volt is applied to the control gates during reading or verify, over-erased cells will conduct slightly, thereby potentially giving an erroneous reading.
The leakage current caused by over-erased cells in a column during a read or verify operation can degrade the performance and reliability of the memory. Ideally, the only cell in the column biased for possible conduction is the cell in the selected word line WL. However, if any of the cells in the selected bit-line or column are over-erased and conduct significant current (i.e., in the sub-threshold conduction region), the combined current flow in the bit-line may exceed the threshold for reading or verify, thereby yielding erroneous results. Leakage current due to over-erased memory cells can also adversely affect the programming of other cells on the same bit-line by reducing the voltage on the bit-line. In some severe situations, a single over-erased cell can disable the entire column. In other cases, many of the cells may be slightly over-erased which provides a cumulative leakage current exceeding the desired threshold.
There are various techniques which can tighten the erased Vt distribution and thus help avoid the "over-erasure" problem. One technique applies iterative erase and verify operations to ensure that the erased threshold voltages of fast-erase cells within the same sector do not become negative. Another technique (referred to herein as a touch-up programming scheme) applies a small amount of programming to all the memory cells after erasure in order to increase the threshold voltages of the fast-erase cells from a slightly negative value to a slightly positive value. A third method programs all the memory cells (the virgin cells) in the sector(s) to a "1" state prior to an erase operation. As a result, the initial threshold voltages of all the memory cells correspond to a "1" state prior to erase. This method can be used in conjunction with the touch-up programming scheme to further reduce the adverse effects of over-erase.
Even with situations where the leakage current is negligible, by using some kind of touch-up programming scheme, the memory cell's characteristics or performance can degrade over time, greatly reducing the reliability and endurance of the device, i.e., the number of cycles that the memory array can be successfully programmed and erased. Repeated erasing and programming of memory cells will cause excessive charge to be trapped in the gate oxide, thereby reducing the performance and endurance of these cells. The endurance of typical Flash memories is over 100,000 program/erase cycles, with some memories capable of 1,000,000 program/erase cycles or more. The increased charge trapped in the gate oxide requires higher programming voltages Vpp and/or longer programming times or pulse duration in order to program a memory cell to the same desired threshold voltage. Similarly, to achieve a desired erased threshold voltage, erase voltages and/or times likewise need to be increased. If program and erase conditions are not properly compensated, continual erasing will cause the margin between a programmed threshold voltage and an erased threshold voltage (or Vt window) to decrease for the affected memory cell. As a result, the sensing margin for read and verify operations decreases. For conventional memories, this will cause access time push-outs, and in analog or multi-bit-per-cell memories, it will lead to decreased dynamic range, poor signal-to-noise ratios, and increased read-out errors. Furthermore, with memory cells that have been subjected to high numbers of erase operations, data can be written to virgin locations within the memory array, which could require a complicated process of tracking virtual and physical addresses.
Thus, it is desirable to reduce the frequency of erase operations and to increase the endurance of non-volatile memories in order to prevent performance degradation and extend the usable lifetime of the memory. As a result, the memory may be used in a much wider range of applications which were previously not practical due to endurance limitations.